Ion implantation is a standard technique for introducing conductivity-altering impurities into a workpiece. A desired impurity material is ionized in an ion source, the ions are accelerated to form an ion beam of prescribed energy, and the ion beam is directed at the surface of the workpiece. The energetic ions in the beam penetrate into the bulk of the workpiece material and are embedded into the crystalline lattice of the workpiece material to form a region of desired conductivity.
The scaling of planar bulk silicon complementary metal oxide semiconductor (CMOS) devices has limitations. For example, at sub-22 nm nodes, the integrated circuit (IC) industry is transitioning to fully depleted (FD) planar or three-dimensional device structures. Doping of these structures using a beam-line ion implanter causes damage to the crystal structure of the silicon, which may not be completely annealed. Active areas in these devices that are damaged or amorphized by ion implantation fail to have the silicon crystal structure restored. This results in degradation of the electrical characteristics in the device. Planar or conformal doping using plasma doping (PLAD) may still introduce some crystal damage. Furthermore, PLAD may produce an oxide or other undesirable films on the workpiece.
Use of a dopant-containing deposited layer also has been attempted. The dopant “drive-in” was performed in a later thermal anneal step. While crystal damage is mostly avoided, a high thermal budget is required and less abrupt dopant profiles are made. This ultimately degrades device performance. Accordingly, there is a need in the art for an improved method of doping, and, more particularly, doping a workpiece using ion bombardment at an elevated temperature.